With the development of science and technology, various chip packages are proposed for various kinds of chips. In these chip packages, a dual flat package (DFP) and a quad flat non-leaded package (QFN), especially in a flip-chip manner, are recently widely used because they have a small thickness, a high integration level and improved heat dissipation. The QFN/DFN flip chip has a first surface facing downward to and being electrically coupled to a carrier pad. The first surface of the chip is an active surface with various electronic devices disposed thereon. The carrier pad may be a large-area intermediate pad of a lead frame, or a printed circuit board (PCB).
Referring now to FIG. 1, a package structure of a conventional QFN/DFN flip chip is shown. As shown in FIG. 1, the package structure 10 of the conventional QFN/DFN flip chip includes a carrier pad 11, a chip 12, a plurality of conductive bumps 13, a molding compound 14 and a plurality of leads 15. The carrier pad 11 has a relatively large area to ensure good heat dissipation performance. The leads 15 are located at edges of the carrier pad 11 and have a thickness the same as that of the carrier pad 11. The chip 12 has an active surface formed with electrodes for various electronic devices. Contact pads (not shown) are formed on the electrodes, corresponding to locations of the electrodes on the active surface. Typically, the contact pads are arranged in an array and are each electrically coupled to the carrier pad 11 or leads 15 by means of conductive bumps 13.
The carrier pad 11 has a uniform thickness anywhere. The conductive bumps 13 have a thickness equal to a distance between the chip 12 and the carrier pad 11. Typically, the conductive bumps 13 are made of copper and have a thickness about 45 micrometers.
The molding compound 14 cannot flow freely between the carrier pad 11 and the chip 12 and cannot completely fill the space between the carrier pad 11 and the chip 12, because the molding compound 14 flows in the space between the carrier pad 11 and the chip 12, which corresponds to gaps between adjacent ones of the conductive bumps 13. Moreover, the chip 12 has a small thickness. Consequently, the chip may be damaged. To solve the problem, one approach is to fill the space between the chip 12 and the carrier pad 11 with an adhesive 16 before encapsulation. The adhesive 16 contains small particles and has good fluidity to ensure a filling effect and solve the problem of fine pitches in the package. As shown in FIG. 1, the adhesive 16 fills the space between the carrier pad 11 and the chip 12, and the molding compound 14 encapsulates other parts of the chip 12.
Nowadays, various chips, including the QFN/DFN flip chip, have a decreased thickness. Underfill is necessary and performed between the carrier pad 11 and the chip 12 before encapsulation to ensure quality of the package. However, underfill will increase package cost and process complexity.
Accordingly, it is an urgent problem for one skilled person to avoid damage of electronic devices in the prior chip package due to a small distance between the chip and the carrier pad and insufficient filling of the molding compound in the space between the chip and the carrier pad.